ADVANCED IC PACKAGING TECHNIQUES : Evolution and Current Trends


“Evolution is the secret of the next step”
Similarly, have you ever thought that there can be evolution in IC packaging? Remarkable, isn’t it?

 Advanced IC packaging is a prominent technology highlight of the “More than Moore” arena. At a time when chip scaling is becoming more difficult and expensive at each node, engineers are putting multiple chips in advanced packages as an alternative to chip scaling.


Let’s get started,

IC packaging is becomes more complex and expensive at each node ,finding challenges and solutions to it is becoming more important. The normal chip designs become more unwieldy that several IC vendors are exploring alternative approaches for packaging ICs. There are some traditional ways to advance chip design and packaging. One way to advance a chip design is to assemble different and advanced dies in a package. Advanced packaging is especially used for higher-end projects, due to cost. IC scaling which is a traditional way of advancing a design, shrinks different chip functions at each node and packs them onto a monolithic die. However, it is becoming too expensive and therefore the benefits are diminishing at each node. While scaling remains an option for designs, the industry is searching for alternatives, which also includes advanced packaging. 

The industry is developing new advanced package types or expanding the prevailing technologies. The fundamental idea behind advance packaging is to cram all chip functions on the same die, break the pieces up and integrate them in a package. This reduces the cost/price and provides better yields. Another option is to bring the chips closer to each other. Many advanced packages bring the memory closer to the processor, which enables faster access to the data with lower latencies. There are several challenges in IC packaging. Also, there is no one package type that fits all needs. The overview of some advanced IC packaging techniques is given below:



Fan-out is expanding into new forms. Among them are:

Fan-out system-in-package (SiP): A SiP is a multi-die package that performs a specific function. A fan-out SIP may incorporate dies and passives. 

A system in package, or SiP, is a way of bundling two or more ICs inside a single package. While SiP saw limited adoption in its forms, there has been much work done on improving this concept recently with 2.5D and 3D-ICs, as well as package-on-package and flip-chips. There are several key drivers for these changes:

  1. Analog IP doesn’t shrink as easily as digital circuits from one process node to the next, making it extremely time-consuming and costly to move IC designs from one process node to the next in accordance to Moore’s Law. Being able to shrink just the digital portions and keep analog at older process geometries is increasingly attractive.
  2.  Shrinking features and adding more functionality onto semiconductors requires longer and thinner wires, which increases the time it takes for signals to move around a chip. By packaging different chips together, connected through an interposer or through-silicon via, those signals can be speeded up using shorter wire distances and wider conduits.
  3.  The need to extend battery life in mobile devices will require ways of reducing the amount of power needed to drive signals. Reducing the distances that signals have to travel, particularly in and out of memory, and increasing the width of the conduits, have a direct effect on the amount of energy expended to drive signals.

 

2.5D/3D: Here, Chips are placed side-by-side or on top of each other in a package. A 2.5D/3D technologies, is a die stacking technique that promises to boost the bandwidth in devices. 2.5D/3D technologies, though, are relatively expensive, limiting the market to high-end applications. 2.5D will continue its slow growth in the HPC (high-performance computing) and automotive sectors for specific applications. However,2.5D/3D technologies have some scaling limitations. There are issues with the bumps/pillars and the tools. In 2.5D/3D technologies, dies incorporate tiny bumps on one side. The bumps on each die are connected using thermal compression bonding (TCB). A TCB bonder uses force and heat to connect the bumps. This is a slow process. The bonding process has a low throughput and cannot overcome the challenge of scaling below a 40μm pitch. Nowadays, most advanced micro bumps and pillars are tiny structures with a 40μm pitch.


If  you want to know more about the terms in advanced IC packaging  do check our blog:


https://basictermsinicpackaging.blogspot.com/



ADVANTAGES OF ADVANCED IC PACKAGING


Advanced IC packaging technologies are pushing printed circuit board (PCB) suppliers towards smaller pitches, better power integrity, and thermal conductivity, to name a few. Shrinking package and board geometries significantly reduces parasitic capacitance and power dissipated in interconnects, resulting in much higher performance per Watt, longer battery life for handheld devices, and lower system cost. Many other electronic systems rely on ICs to increase the number and quality of features, improve safety, reliability, and enable user-friendly operation. Lower power consumption because of their smaller size.



IC PACKAGING EVOLUTION SINCE 1970’s.





ADVANCED PACKAGING MARKET SHARE EVOLUTION 2014-2025


In 2014, AP market share was 38% and there is strong possibility that in 2026, AP market share will exceed that of traditional packaging. In 2019, the AP market share was 42.6%. Due to strong momentum in AP market driven by mega trends, the share of AP in the total semiconductor market is increasing continuously and will reach almost 50% of the market by 2025.Advanced Packaging revenue will almost equal to traditional packaging revenue by 2025.


Packaging technology plays an important role in the realisation of a new generation of products. This requires the development of new packaging technologies and materials. The estimation of packaging technologies can be done by an indicator the so called packaging efficiency. It is defined by the ratio of the silicon chip to the area of the package. The best level of efficiency for peripheral packages, like QFP, can reach 50%; for area array package like BGA/CSP does not exceed 90% and for wafer scale or bare chip solutions can achieve 100% silicon efficiency.



CURRENT TRENDS IN ADVANCED IC PACKAGING



The development of the electronics industry is dominated by communication products, which are characterized by rapid market introduction and fast mass-manufacturing capabilities. The main drivers of this development are miniaturization and styling or eco design and production. The industry has made great strides in reducing the package size from the dual in line package (DIP) and quad flat pack (QFP) to ball grid array (BGA) and chip scale t package (CSP). Standard lead frame packages still have the largest market share. Packages like BGA and CSP have gained increasing importance and popularity.

Let's Summarise


In this blog, we covered all that you need to know about advanced IC packaging. We gave an overview of some advanced IC packaging techniques and several key factors that are driving this change. We discussed the advantages of these advanced IC packaging techniques as well as the evolution of IC packaging from 1970 to 2025.We also discussed about the current trends in the advanced IC packaging market.



“The only constant in life is change”-Heraclitus.

References:


https://www.edn.com/lost-in-the-advanced-ic-packaging-labyrinth-know-these-10-basic-terms/


https://www.edn.com/heterogeneous-integration-and-the-evolution-of-ic-packaging/


https://semiengineering.com/five-trends-in-ic-packaging/


https://www.semiconductors.org/wp-content/uploads/2020/09/Santosh-


Kumar_Yole_Advanced-Packaging-Current-Trends-and-Challenges.pdf



AUTHOR: RIYA KAKTIKAR



We hope you’ve enjoyed reading this blog. In case of queries, Please feel free to drop your queries in the comment section

Comments

  1. Replies
    1. Thanks for showing interest, highly appreciated!

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  2. Replies
    1. Thanks for showing interest, highly appreciated!

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  3. Replies
    1. Thanks for showing interest, highly appreciated!

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  4. Replies
    1. Thanks for showing interest, highly appreciated!

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    1. Thanks for showing interest, highly appreciated!

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  6. Grear work !
    Informative content

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    1. Thanks for showing interest, highly appreciated!

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    1. Thanks for showing interest, highly appreciated!

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  8. Great work! extremely informative 👍👍

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    Replies
    1. Thanks for showing interest, highly appreciated!

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  9. Replies
    1. Thanks for showing interest, highly appreciated!

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  10. Great article Riya ! How do you think these trends will influence the industry in the next decade.

    ReplyDelete
    Replies
    1. New advanced IC packaging technologies wil provide greater silicon integration in increasingly miniaturized packages which will provide solutions that deliver more functionality, added performance, higher speed, and smaller form factors.
      Thank you for showing interest, highly appreciated!!

      Delete
  11. Would like to know more about the recent developements in this field! Keep us posted.:)

    ReplyDelete
    Replies
    1. Thanks for showing interest, highly appreciated!
      Will definitely write an article dedicated to this topic. You can check the links mentioned in the blog for more information and news related to Advanced IC packaging.

      Delete
  12. Worth the read!! Would love to know more about the impact trends have created.

    ReplyDelete
    Replies


    1. Thanks for showing interest, highly appreciated!
      Will definitely write an article dedicated to this topic. You can check the links mentioned in the blog for more information and news related to Advanced IC packaging.

      Delete
  13. Replies
    1. Thanks for showing interest, highly appreciated!

      Delete
  14. Thanks for showing interest, highly appreciated!

    ReplyDelete
  15. Very Informative and well articulated!!

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